Exemplary embodiments of the present invention relate to a command control circuit, an integrated circuit having the same, and a command control method.
Parity check refers to a technology for checking whether transmission data has been lost or damaged at the time of data transmission. Other technologies for checking whether transmission data has been lost or damaged at the time of data transmission includes use of cyclic redundancy check (CRC), etc.
In performing a parity check, a parity bit is added to a bit sequence and transmitted. The parity bit is used for checking whether transmitted bits have been successively transferred.
An exemplary method for performing parity check is as follows. If the sum of all data bits is even before they are transmitted, a parity bit is set to 1 so that the total sum of the transmitted bits is odd. If the sum of the data bits is already odd, the parity bit is set to 0. A data receiving side checks whether the sum of all bits is odd. If the sum of the bits is even, it represents that an error has occurred during data transmission. Thus, corresponding data is retransmitted or a system is stopped and an error message is sent to a user.
An integrated circuit may use parity check in order to substantially prevent an abnormal operation from being performed due to an error or distortion on an interface. Parity check is used when an error rate is low. An integrated circuit may detect an erroneous command using the parity check.
FIG. 1 is a block diagram of a conventional integrated circuit.
As illustrated in FIG. 1, the integrated circuit includes a command input unit 110, an address input unit 120, a clock buffer 130, a check data input unit 140, an error check unit 150, a synchronization unit 160, a synchronization delay unit 170 and a command decoder 180.
The error check unit checks an error of a command CMD and an address ADD. The synchronization unit 160 allows an error check result to be synchronized with a clock CLK, and includes a pipe latch. The synchronization delay unit 170 delays the command CMD and the address ADD. The command decoder 180 decodes a delay command DEL_CMD to generate an internal command IN_CMD.
The operation of the integrated circuit will be described with reference to FIG. 1 below.
The command input unit 110 receives the command CMD in synchronization with a clock CLK inputted from the clock buffer 130. The command CMD includes a row address strobe (RAS) signal, a column address strobe (CAS) signal, a write enable (WE) signal, and a chip select (CS) signal. The address input unit 120 receives the address ADD in synchronization with the clock CLK. The check data input unit 140 receives check data CHE_DATA in synchronization with the clock CLK.
The synchronization delay unit 170 delays the command CMD and the address ADD in synchronization with the clock CLK to generate the delay command DEL_CMD and a delay address DEL_ADD. In order for the command decoder 180 to determine whether an error exists in the command CMD and the address ADD and generate the internal command IN_CMD, it is desired that the command CMD, the address ADD and an error check signal ERR arrive at the command decoder 180 within a certain window of time. However, since an error check operation of the error check unit 150 takes some time, the command CMD and the address ADD are to be delayed in order to allow the command CMD, the address ADD and the error check signal ERR indicating the presence or absence of an error to arrive at the command decoder 180 simultaneously. Here, the synchronization unit 160 has a delay in transmitting a signal in response to its inputs. Delay information DEL<0:1> is used to determine the delay time of the command CMD and the address ADD. The number of flip-flops 171 to 174 used to delay the command CMD and the address ADD is determined according to the values of the delay information DEL<0:1>.
The error check unit 150 checks whether an error exists in the command CMD and the address ADD by using the check data CHE_DATA, and generates a check result signal CHECK_RES having different values according to an error check result. The error check unit 150 operates asynchronously with the clock CLK and generates a valid signal VALID representing that the error check result is valid.
The synchronization unit 160 stores the check result signal CHECK_RES in response to the valid signal VALID and generates an error check signal ERR by using the check result signal CHECK_RES in response to a delayed internal signal ICST in synchronization with the clock CLK. Here, timing points at which the delay command DEL_CMD and the error check signal ERR reach the command decoder 180 coincide with each other. The internal signal ICST is obtained by delaying the command CMD in synchronization with the clock CLK.
The command decoder 180 decodes the delay command DEL_CMD to generate the internal command IN_CMD. At this time, the decoding operation of the command decoder 180 is performed in synchronization with the clock CLK. When an error exists in the command CMD or the address ADD, the command decoder 180 does not activate the internal command IN_CMD according to the error check signal ERR. When no error exists in the command CMD and the address ADD, the command decoder 180 activates the internal command IN_CMD.
A check operation signal CHECK is used to determine whether to perform the error check operation. When the check operation signal CHECK is deactivated, the error check unit 150 does not operate the error check operation and the synchronization delay unit 170 does not delay the command CMD and the address ADD. The values of the delay information DEL<0:1> and the check operation signal CHECK are determined by MRS setting.
Since the command decoder 180 operates in synchronization with the clock CLK, the delay command DEL_CMD and the error check signal ERR inputted to the command decoder 180 are to be synchronized with the clock CLK. Thus, the synchronization delay unit 170 uses a plurality of flip-flops 171 to 174 in order to delay the command CMD and the address ADD in synchronization with the clock CLK. As the number of commands CMD and addresses ADD is increased, the number of flip-flops for delaying respective ones of the commands CMD and the addresses ADD also increase, and thus an increase in a circuit area and power consumption in implementation may result.